@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MF104 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":85:7:85:21|Found compile point of type hard on View view:ctu_can_fd_rtl.inf_ram_wrapper_32_128_12_true_true(rtl) 
@N: MF104 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_core.vhd":100:7:100:14|Found compile point of type hard on View view:ctu_can_fd_rtl.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl) 
@N: MF104 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd":103:7:103:19|Found compile point of type hard on View view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) 
@N: MF105 |Performing bottom-up mapping of Compile point view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) 
@N: MF106 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd":103:7:103:19|Mapping Compile point view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) because 
@N: MO106 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":628:17:628:22|Found ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) with 16 words by 5 bits.
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":235:12:235:13|RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":235:12:235:13|RAM txt_buf_comp_gen\.6\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":235:12:235:13|RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":235:12:235:13|RAM txt_buf_comp_gen\.4\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":235:12:235:13|RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":235:12:235:13|RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":235:12:235:13|RAM txt_buf_comp_gen\.7\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd":235:12:235:13|RAM txt_buf_comp_gen\.5\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_ram.vhd":237:12:237:13|RAM rx_buffer_inst.rx_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 128 words by 1 bits.
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_pointers.vhd":285:8:285:9|Found counter in view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) instance rx_buffer_inst.rx_buffer_pointers_inst.write_pointer_raw_i[6:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_pointers.vhd":308:8:308:9|Found counter in view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) instance rx_buffer_inst.rx_buffer_pointers_inst.write_pointer_ts_i[6:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":699:8:699:9|Found counter in view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) instance rx_buffer_inst.read_counter_q[4:0] 
@N: MF179 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd":356:14:356:48|Found 32 by 32 bit equality operator ('==') tx_arbitrator_inst.less_than\.un6_timestamp_valid (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl))
@N: MF179 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_filter.vhd":130:27:130:53|Found 29 by 29 bit equality operator ('==') gen_filt_pos\.valid (in view: ctu_can_fd_rtl.bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl))
@N: MO225 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/operation_control.vhd":227:8:227:9|There are no possible illegal states for state machine operation_control_inst.curr_state[0:3] (in view: ctu_can_fd_rtl.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl)); safe FSM implementation is not required.
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd":192:8:192:9|Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_1(rtl) instance tq_counter_q[7:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd":223:8:223:9|Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_1(rtl) instance segm_counter_q[8:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd":192:8:192:9|Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_0(rtl) instance tq_counter_q[7:0] 
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd":223:8:223:9|Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_0(rtl) instance segm_counter_q[8:0] 
@N: MF135 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_data_cache.vhd":189:8:189:9|RAM tx_data_cache_inst.tx_cache (in view: ctu_can_fd_rtl.bus_sampling_255_8_7_8_true_15(rtl)) is 8 words by 1 bits.
@N: MO231 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ssp_generator.vhd":213:8:213:9|Found counter in view:ctu_can_fd_rtl.ssp_generator_15(rtl) instance btmc_q[14:0] 
@N: FX271 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd":1152:8:1152:9|Replicating instance memory_registers_inst.txtb_sw_cmd\.set_abt (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) with 32 loads 2 times to improve timing.
@N: FX271 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_fsm.vhd":208:8:208:9|Replicating instance prescaler_inst.bit_time_fsm_inst.current_state[0] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) with 31 loads 2 times to improve timing.
@N: FX271 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":170:24:170:25|Replicating instance memory_registers_inst.control_registers_reg_map_comp.mode_reg_comp.reg_value_r[10] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) with 35 loads 3 times to improve timing.
@N: FX271 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd":170:24:170:25|Replicating instance memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[14] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) with 13 loads 1 time to improve timing.
@N: MT615 |Found clock SYS_CLK with period 10.00ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
